Simple custom pass in yosys

Tags: / tools electronics /

A simple custom yosys.

For use with yosys (link).

Input verilog file

Suppose that we got a verilog file adder.v for a half-adder like

module halfadder (a, b, sum, carry);
    input a, b;
    output sum, carry;
    wire sum, carry;

    xor(sum, a, b);
    and(carry, a, b);
endmodule

Creating a custom pass

Create a directory named mypass/ under the passes/ directory and create a file mypass.cc with the following:

#include "kernel/yosys.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct MyPass : public Pass {
    MyPass() : Pass("MyPass","counter") { }

    void execute(vector<string>, RTLIL::Design *design) override
    {
        log("Inside the newly created pass\n");
        log_header(design, "Executing MyPass\n");
        for (auto mod : design->modules())
        {
            log("  %s (%d wires, %d cells)\n", log_id(mod),
                    GetSize(mod->wires()), GetSize(mod->cells()));
            run_pass("dump",*&design);
        }
    }
} MyPass;
PRIVATE_NAMESPACE_END

Synthesizing gate-level netlist

We convert behavioural verilog code into gate-level netlist here.

Create a file named script.ys (just a random name) with the following yosys commands:

# Read verilog source and convert to an internal representation
read_verilog adder.v

# Elaborate design hierarchy??
hierarchy -check -top adder

# Convert high-level behavioural constructs (processes) to D-flip flops and MUXes
proc

# Analyze and optimize FSMs
fsm

# Optimizations
opt

# Analyze memories and create their circuit implementations
memory                                                  

# Optimizations
opt

# Convert design to logical gate-level netlists (like adders to logic gates)
techmap

# Optimizations
opt

# Map registers to the hardware flip flops available from the cell library
dfflibmap -liberty examples/cmos/cmos_cells.lib

# Map remaining logic to cell library cells
abc -liberty examples/cmos/cmos_cells.lib

# Cleanup (just last step of opt)
clean

# Write results to output file
write_verilog synth.v

and run them with yosys using

yosys -s script.ys

This will create a synth.v file with the netlist in it.

We are using a cell library named cmos_cells.lib from the examples/ directory of the yosys source code.

Running the custom pass

Use

yosys-config --build hello.so hello.cc

and a file named hello.so would get created.

Now use the synth.v file that got generated earlier and run

yosys -ql hello.log -m hello.so synth.v -p MyPass

to get the log data in the file hello.log.

References