Flip-flops and registers

• Date created: ??-May-2021

Types of flip-flops

SR

‘S’ and ‘R’ stands for ‘Set’ and ‘Reset’ respectively.

S   R   Qₙ  Qₙ₊₁  
----------------  
0   0   0    0    (no change)
0   0   1    1    (no change)
0   1   0    0    (reset)
0   1   1    0    (reset)
1   0   0    1    (set)
1   0   1    1    (set)
1   1   x    ?    (not allowed)

JK

The J and K in the name of the flip-flop doesn’t have an expansion and was apparently chosen randomly (except that they are adjacent letters in the English alphabet).

J   K   Qₙ  Qₙ₊₁  
----------------  
0   0   0    0    (no change)
0   0   1    1    (no change)
0   1   0    0    (reset)
0   1   1    0    (reset)
1   0   0    1    (set)
1   0   1    1    (set)
1   1   0    1    (toggle)
1   1   1    0    (toggle)

T

T stands for ‘toggle’.

T   Qₙ  Qₙ₊₁  
------------  
0   0    0    (no change)
0   1    1    (no change)
1   0    1    (toggle)
1   1    0    (toggle)

T flip-flop can be implemented by applying same signal to J and K inputs of a JK flip-flop.

            --------
            |      |
T ->----->--|J   Q |--->
      |     |      |
      v     |      |
      |     |      |
      --->--|K   Q'|--->
            |      |
            --------

D

D stands for ‘delay’.

D   Qₙ  Qₙ₊₁  
------------  
0   0    0    (no change)
0   1    1    (no change)
1   0    1    (toggle)
1   1    0    (toggle)

D flip-flop can be implemented with a JK flip-flop by applying the input signal at J and its complement at K.

             --------
             |      |
D ->----->---|J   Q |--->
      |      |      |
      v      |      |
   -------   |      |
   | NOT |   |      |
   -------   |      |
      |      |      |
      v      |      |
      --->---|K   Q'|--->
             |      |
             --------

Registers

Consists of a set of flip-flops.

Shift registers

Consists of a number of (cascaded) flip-flops that share a clock signal.

Output of a flip-flop is connected to the input of another flip-flop.

Data access could be of one of the following:

• Serial-in parallel-out (SIPO)
• Parallel-in serial-out (PISO)

Ring Counters

Output of last flip-flop connected input of the first, making a circular (or ‘ring’) counter.

aka:

• straight ring counter
• one-hot counter

Disadvantages

• Needs to ‘inject’ a first state
• Lesser code density (ie, lesser number of states (n states))

A 4-bit (straight, ie not twisted) ring counter.

 State | Q0 | Q1 | Q2 | Q3
-------|----|----|----|----
   0   | 1  | 0  | 0  | 0  
   1   | 0  | 1  | 0  | 0  
   2   | 0  | 0  | 1  | 0  
   3   | 0  | 0  | 0  | 1  
   0   | 1  | 0  | 0  | 0  

Johnson counter

Complement of output of last flip-flop is connected to the input of the first flip-flop.

Advantages

• No need to ‘inject’ first state
• Higher code density (ie, more number of states)
• Hamming distance between any two adjacent states = 1

aka:

• ‘Twisted ring counter’.
• Switch-tail ring counter
• Walking ring counter
• Mobius counter

4 bit Johnson counter

 State | Q0 | Q1 | Q2 | Q3
-------|----|----|----|----
   0   | 0  | 0  | 0  | 0  
   1   | 1  | 0  | 0  | 0  
   2   | 1  | 1  | 0  | 0  
   3   | 1  | 1  | 1  | 0  
   4   | 1  | 1  | 1  | 1  
   5   | 0  | 1  | 1  | 1  
   6   | 0  | 0  | 1  | 1  
   7   | 0  | 0  | 0  | 1  
   0   | 0  | 0  | 0  | 0  

Edge triggered flip-flops

• Positive edge triggered flip-flops change state during a 0 → 1 transition of the clock (ie, rising edge of the clock).
• Negative edge triggered flip-flops change state during a 1 → 0 transition of the clock (ie, falling edge of the clock).

Todo

• Latch
• Flip-flop
• Setup time
• Hold time
• Recovery time
• Removal time
• Aperture
• Propagation delay

References

• Switching Theory and Finite Automata (Third edition) by Zvi Kohavi, Niraj K. Jha
• https://en.wikipedia.org/wiki/Flip-flop_(electronics)