Bluespec SystemVerilog

Bluespec SystemVerilog (BSV) is different from Bluespec Haskell (BH). But both are implementations of Bluespec.

• One rule at a time.

• Higher abstraction level.

• proviso: something related to type classes

  • type classes are there as well.

Interfaces

• Advertises the outside facing part of a module.
• The methods present in the interface are the only ways of accessing the module. Including feeding input and retrieving output.
• Empty: the (predefined) empty interface

Assignment operations

• <-
  • Action assign
  • Use when instantiating a module
    • In fact, for any interface method returning a value.
• <=
  • Non-blocking
  • Eg: Register assignment
• =
  • Zero-time
  • Just like a wire.

Macros

Define like:

'define <macroname> <macrobody>

and use like:

'<macroname>

(Or is it backtick ??)

Textual replacement, I guess.

SystemVerilog has this as wellʳ.

Include external files

One of the following syntaxes:

• All effectively same.
• Relative path names are fine.
• The .bsv extension is apprently needed.

'include "filename"
'include <filename>

Methods

Tuples

• 2-tuple (tuple2) to 7-tuple (tuple7) available
• Extract particular elements of tuple with tpl_1 (like fst in sml), tpl_2 (like snd in sml), …, tpl_7.
• Types are Tuple<n>, constructors are tuple(...)

// Type of tuple of 2 Bit values
typedef Tuple2 #(Bit #(1), Bit #(1)) B2;

// A value of B2 type
B2 ab = tuple2(1'b1, 1'b0);

Values of a tuple can also be taken out with pattern matching:

Tuple3#(int, bool, int) ibi = tuple3(0, true, 1);

case (ibi) matches
  {.a, .b, .c} : (b ? a : c)
endcase

Useful functions

Usual functional programming style functions available. Some standard libraries may need to be imported for some of them to be used.

• zipWith
• map
• scanl, sscanl

Compiling

• -g: specify top-level module name
• -e: specify top-level when linking
• -u: specify dependency packages
• -show-schedule: show generated schedule
• -sched-dot: generate dot file showing the way rules were scheduled.
  • Use -info-dir to specify directory to which this dot file should be placed.
  • Separate graphs are generated for each module.
    • <module>_conflict.dot
    • <module>_exec.dot (execution order)
    • <module>_urgency.dot
    • <module>_combined.dot
    • <module>_combined_full.dot

Misc

• ?: 'a special don't care value'
• KPNS (shown in some compiler errors): Known problems and solutions
• Ternary operator available: ((s == 0) ? a : b)
• begin and end can be used to demarcarte code blocks. Like { and } in C.
• bluesim: tool to simulate designs made in bsv
• .bs: extension of BSH files (Haskell-like)
  • Eg: https://github.com/B-Lang-org/bsc/blob/main/src/Libraries/Base2/Wallace.bs
• Action: 'an expression intended to act on the state of the circuit'
• Integer is unsynthesizable, but is often used for loops because the loop would be unrolled in the elaboration phase anyway.
• valueOf and valueof are equivalent.
• 'modules and interfaces turn into actual hardware'. They form the 'heart of BSV'.
• 'rules are the fundamental means to express behavior in BSV'
• Use $finish (0); to end a simulation instead of letting it loop forever.
• scan family of functions applies a function over a list, creating a new List result. The scan function is similar to fold, but the intermediate results are saved and returned in a list, instead of returning just the last result.' ʳ
  • Like scanl: (a -> b -> a) -> a -> [b] -> [a]
• pack and unpack are available if value's type belongs to the Bit typeclass.
  • pack: convert to Bit#() form
  • unpack: convert from Bit#() form
• 'A module can be annotated with the synthesize attribute' ʳ. This has the same effect as passing the module name to compiler with the -g flag.

(* synthesize *)
module mkFoo (FooIfc);
...
endmodule

References and links

• Reference guide (2010)
• User guide (2008):
• Wiki: http://wiki.bluespec.com/Home/BSV-Documentation
• BSV by example: http://csg.csail.mit.edu/6.375/6_375_2019_www/resources/bsv_by_example.pdf

• https://github.com/B-Lang-org/bsc/discussions/603
• bluecheck: Like Quickcheck, apparently no longer maintained

Papers:

• R. Nikhil, "Bluespec System Verilog: efficient, correct RTL from high level specifications," Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04., San Diego, CA, USA, 2004, pp. 69-70, doi: 10.1109/MEMCOD.2004.1459818.
• Rishiyur S. Nikhil and Arvind. 2008. What is Bluespec? SIGDA Newsl. 38, 23 (December 2008), 1. https://doi.org/10.1145/1862867.1862868