Originally seemed to have meant 'Tool Command Language'.
Popular with EDA tools
tclsh: a simple tcl interpreter
foreach elem in [seqvar]
$
signset
??set outputDir ./my_dir
file mkdir $outputDir
#
.https://wiki.tcl-lang.org/page/comment
file delete file1 file2
file delete -force <dirname>
https://stackoverflow.com/questions/24376421/passing-arguments-from-command-line-into-a-tcl-script
argc
: number of command line arguments
argv
: command line arguments
lindex $argv 0
argv0
: name of script (as in $argv0
)
indexing a list: lindex
puts
)# A newline is added by default
puts "hello world"
%
hello world
# Use -nonewline to skip the new line
puts -nonewline "hello world"
% hello world%
See: https://wiki.tcl-lang.org/page/Tcl+cheat+sheet
proc
)This is how new commands are made in tcl.
proc say_hello {} {
puts "Hello!"
}
% say_hello Hello!
Or with an argument:
proc say_hello name {
puts "Hello $name!"
}
"Jack"
% say_hello Hello Jack!
Or with multiple arguments:
proc say_hello {fname lname} {
puts "Hello $fname $lname!"
}
"Jack" "Sparrow"
% say_hello Hello Jack Sparrow!
See:
Launch (no gui, but with tcl prompt): vivado -mode tcl
source name.tcl
to load a tcl file interactivelylaunch in batch mode (no gui, no tcl prompt): vivado -mode batch -source filename.tcl
tcl console:
start_gui
stop_gui
Globbing in paths: [ glob ./src/hdl/*.vhdl ]
Read source file:
read_verilog top.v
-sv
for systemverilogread_vhdl
read_edif
: netlist. Usable for proprietary IPs ??read_ip
: useful for core generators (xco, xci)synthdesign: synthesis
optdesign: optimizations ??
poweroptdesign: (optional)
placedesign: placing
physoptdesign: (optional)
routedesign: routing
writecheckpoint
opencheckpoint: open a previously save dcp file
launchrun: launch a run that was previously created
set_property
before runningcreaterun: create a run
reportdesignanalysis
Checkpoint: netlist at a particular stage of the EDA process
Reports
writeverilog: write the netlist at its current stage as verilog
writexdc: write the constraints which were used during routing
writebitstream: generate bitstream
remove_files PYNQ-Z2_3pin.xdc
: remove a file that was added to project
—
—
# https://github.com/ATaylorCEngFIET/mz_428/blob/master/project/project-flow.tcl
# https://www.adiuvoengineering.com/post/microzed-chronicles-scripting-vivado
# start_gui
-part xc7k160tffv676-1
create_project hello /media/julinusername/zwei/data/vivado_projs/hello -norecurse /home/julinusername/verilog/Demo.topEntity/topEntity.v
add_files[current_fileset]
set_property top topEntity -fileset sources_1
update_compile_order1 -jobs 8
launch_runs synth_1
wait_on_run synth_1 -jobs 8 -to_step write_bitstream
launch_runs impl_1 wait_on_run impl_