• always: statements inside in these blocks are executed sequentially ʳ
  • always @(<sensitivity-list>): fire if any signal in sensitivity list changes
  • always @(*): means all input included
  • Executed repeatedly throughout the simulation
  • Use always block with care. Make sure that no two always blocks are in conflict. Otherwise unexpected behaviour can pop up.
• repeat(n): replicate a block n times
• `timescale <time_unit>/<time_precision>
  • `timescale 1ns/1ps: says 1 step is 1ns and I guess to report with precision upto 1ps
  • Specified for the benefit of simulator
  • Units of time usable: s, ms, us, ns, ps or fs
  • https://www.chipverify.com/verilog/verilog-timescale
  • This is a compiler directive
• Modules, wires, registers
• posedge <signal>, negedge <signal>: positive & negative edge of a signal respectively
  • eg: always @(posedge clk or negedge rst) begin ... end
  • I guess posedge is like rising_edge(signal) in VHDL
• begin .. end is not needed if there's only one statement
• function vs task: task can take up simulation time, unlike function
  • Tasks are generally non-synthesizable
• logic: apparently same as reg
  • https://electronics.stackexchange.com/questions/331393/what-is-the-difference-between-logic-reg-and-wire-in-system-verilog-explainati
  • https://chipmunklogic.com/digital-logic-design/logic-vs-wire-in-system-verilog-some-misconceptions/
• >>> vs >>: >>> copies sign bit. >> fills in with 0
  • Looks like there's no <<<, which sounds meaningless anyway.
• $unsigned(v): type cast to unsigned
• casex and casez: case with wildcards allowed
  • https://www.verilogpro.com/verilog-case-casez-casex/
• unique, priority modifiers: ??
  • https://www.verilogpro.com/systemverilog-unique-priority/
• 64'sd1: a 64 bit signed decimal constant of value 1

Signal strengths

• 4 driving strengths
• 3 capacitative strengths
• 1 high impedence

Table from here:

• Strength of a net is the strength of its highest driving signal.
• High impedence is like when there is an open circuit ??
  • https://stackoverflow.com/questions/49987012/the-difference-between-x-and-z

See:

• https://web.archive.org/web/20201022054201/https://verilog.renerta.com/source/vrg00047.htm
• https://www.hdlworks.com/hdl_corner/verilog_ref/items/Strengths.htm
• https://vlsiverify.com/verilog/strength-in-verilog/

—

Signal states ??

In simulation, all values start with x by default.

initial block

• Starts execution immediately
• Each statement in the block is executed one after the other, not concurrently
• The entire block runs only once
  • Unlike always block
• There can be multiple initial blocks??
• initial blocks are not synthesizable (generally)

https://www.pace.edu.in/img/course/Verilog_HDL_Module4.pdf

Assignments

• Blocking: =
• non-blocking: <=

General

• Comment: As in C
  • Single line: //
  • Multi-line: /* ... */
• Values:
  • z: high impedence
  • x: unknown/uninitialized
  • 0: logic 0
  • 1: logic 1
• localparam: similar to parameter but cannot be modified by module instance argument or with defparam
  • https://stackoverflow.com/questions/30288783/difference-between-parameter-and-localparam

Literals

Format: n'bVAL:

• n: number of bits
• b: base
• VAL: value

Default is base is decimal.

• 8'hFF: 8-bit hex number of value FF (ie, 0xFF)
• 5'b101: 5-bit binary number (ie, 0b00101)
• 1: decimal number
• 3'o5: 3-bit octal number (ie, 0o5)

https://users.ece.utexas.edu/~patt/04s.382N/tutorial/verilog_manual.html

Compiler directives

• Starts with a backtick.
• Eg: `define, `include, `ifdef .. else .. `endif,
• `include "file.v": include another verilog file
• `define: make text macros (à la C)

See:

• https://vlsiverify.com/verilog/compiler-directives/
• https://users.ece.utexas.edu/~patt/04s.382N/tutorial/verilog_manual.html

Macros

• C-style macros
• Textual replacement

// word size
`define wsize 32
`define word [`wsize-1:0]
...
...
input `word a, b;

Operators

• Conditional operator (ternary): ?:
  • cond ? true : false
• Shifting: << and >>
• Concatenation
  • Possible for any sized value
  • Syntax: comma seperated values inside curly braces
  • Eg: {1'b0, 1'b1, 1'b0} gives 3'b010
  • Provision for repetition available: {2 {expr}} is same as {expr, expr}
    • Eg: {2 {1'b0}, 1'b1} is 3'b001
    • assign {c_out, sum} = a + b + c_in; (in full adder)

Bitwise operators

Reduction operators

• These operators are unary.
• Kind of like a fold
  • Eg: Reduction AND does AND of all bits in operand vector

Indexing into vectors

Possible for sized values like vectors ??

Bit-select

'Indexing' into a vector/similar

Example:

wire [7:0] a;

// 0th bit of a
a[0]

// 4th bit of a
a[4]

Part-select

'Slicing a vector/similar

Example:

wire [7:0] a;

// 2nd, 1st and 0th bits of a
a[2:0]

// 5th, 4th and 3rd bits of a
a[5:3]

System tasks

• $dumpfile("name.vcd"): dump wave info as vcd
• $dumpvars(number_of_levels, instance_name): dump wave info as vcd
  • level_count = 0: dump all signals at all levels of the instance
  • level_count = 1: only dump signals at top level
  • level_count = n: dump signals n level hierarchically below named instance ??
• $readmemb("filename", instance_name.mem, starting_addr): read from a binary file ??
• $readmemh("filename", instance_name.mem, starting_addr): read from a hex file ??
• $strobe: print messages on screen after end of current time slot (postpone region)
  • Like printf in C
  • Eg: $strobe()
• $display: print messages (active region)
• $write: like $display, but no newline
• $time: returns current simulation time
• $finish: end simulation

See:

• https://users.ece.utexas.edu/~patt/04s.382N/tutorial/verilog_manual.html

specify blocks

• A relatively obscure part of verilog..

• 'Defines a delay across a module'

• Delays are mentioned in picoseconds

• A => B = 12: simple combinationational path from A to B with delay 12ps

See:

• https://www.hdlworks.com/hdl_corner/verilog_ref/items/Specify.htm
• https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html

Misc

• bufif0, bufif1, notif0, buf
  • https://vlsiverify.com/verilog/gate-level-modeling/
  • https://peterfab.com/ref/verilog/verilog_renerta/mobile/source/vrg00003.htm
• trireg nets
• drive strength vs charge strength

iverilog

• Find directory of vpi modules: iverilog-vpi --install-dir ʳ

Tips

• Delay in synthetically verilog ??
  • Count clock as per operating frequency
• How to find operating frequency of a design loaded onto fpga? Is that a constraint?

DBT

• Postpone region
• Active region
• Can this be made a one-liner?

temp[0] <= a^b;
temp[1] <= a&b;

• How to drive RGB output
• How to circularly shift a 1 in a vector
• Worst negative slack is 4.002ns, but total negative slack is 0.000ns ??
• what colour if 11 is written to an rgb led?

Splitting long lines

This works:

// Verilog
module full_adder (
  input a, b, cin,
  output s, cout
);

  assign s = a ^ b ^ cin;
  assign cout =
      (a & b)
    | (b & cin)
    | (cin & a);
endmodule

Links

• IEEE standard for SystemVerilog: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8299595

SystemVerilog

• Function: function <name> (args); <body> endfunction
  • Arguments can have default values
• Array
  • Declaration: <type> <name> [<size>];
  • Size of array: $size <name>
• for loop: for(int i=0; i<5; i++) begin ... end
  • Kinda like in C
• .svh: like header files for SystemVerilog source

Stuff not in verilog:

• === and !==
• ++, -- (incr/decr)
• +=, -= (assignment)
• always_ff, always_comb, always_latch
  • https://www.verilogpro.com/systemverilog-always_comb-always_ff/
• priorty, unique
  • Kind of like parallel_case and full_case pragmas in verilog ??
• interface
• https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-rtl-tutorial/

enum type

typedef enum {red, green, blue} Colour;

typedef enum {red=10, green=20, blue=30} Colours;

always stuff

• always_comb: a combinatory block
  • sensitisation list can be inferred automatically if all used signals are there ??
• always_ff: infer 'transparent flip flip'
• always_latch: infer 'transparent latch'

Verilog's always block was less expressive. Specialized blocks convey the meaning more clearly.

Associative array

• Like python dictionaries
• Declaration syntax: <val_type> <name> [<index_type>];

// Assoc array with string index and int values
int fruitprice[string];

fruitprice = '{"Apple": 190,
               "Orange": 120};

See: https://www.chipverify.com/systemverilog/systemverilog-associative-array

Classes

https://www.chipverify.com/systemverilog/systemverilog-class

• Syntax is kind of like JavaScript classes.
• this: current object (or is it class??)
• function new (): constructor
  • Auto invoked on object creation
• Inheritance: extends
  • Eg: class subclass extends baseclass;
  • Invoke superclass attribute: super.<attribute>
• virtual class: abstract class
  • Can only be extended.
  • Cannot be instantiated.

Command line arguments

• Can be passed to simulation with a + character

• These arguments are accessible with plusargs functions

• https://www.chipverify.com/systemverilog/systemverilog-command-line-input

• $test$plusargs (str): Check if the argument str exists ??

• $value$plusargs (str, var)

  • Like $test$plusargs but also gets value associated with argument str to var

Constraints

• Kind of like refined types
• Useful during verification/testing

bit [7:0] addr;
constraint addr_limit { addr <= 8'hB; }

https://www.chipverify.com/systemverilog/systemverilog-constraints

Coverage

• coverpoint: variables
• covergroup block: groups cover points

https://www.chipverify.com/systemverilog/systemverilog-functional-coverage

iverilog

Apparently, iverilog doesn't consider input as systemverilog by default. Got to use -g2005-sv.

$ iverilog -g mem.sv 
Unknown/Unsupported Language generation mem.sv

Supported generations are:
    1995    -- IEEE1364-1995
    2001    -- IEEE1364-2001
    2005    -- IEEE1364-2005
    2005-sv -- IEEE1800-2005
    2009    -- IEEE1800-2009
    2012    -- IEEE1800-2012
Other generation flags:
    assertions | supported-assertions | no-assertions
    specify | no-specify
    verilog-ams | no-verilog-ams
    std-include | no-std-include
    relative-include | no-relative-include
    xtypes | no-xtypes
    icarus-misc | no-icarus-misc
    io-range-error | no-io-range-error
    strict-ca-eval | no-strict-ca-eval
    strict-expr-width | no-strict-expr-width
    shared-loop-index | no-shared-loop-index

$ iverilog -g2005-sv mem.sv 

Parenthesis in if condition

Looks like boolean expressions serving as conditions for if always need to be enclosed within parenthesis.

This works:

if (en_wr)

but this doesn't

if en_wr

Macros

Execute only if a macro is defined:

`ifdef MACRO_NAME

`endif