VHDL

VHDL is:

• Strongly typed.
• Case insensitive (unlike verilog).
• Full form: VHSIC Hardware Description Language
  • where VHSIC is Very High Speed Integrated Circuits
• Named after the US DoD project that created it: VHSIC program

Comments

Part of a line that comes after a --.

Reserved words

Reference: https://www.seas.upenn.edu/~ese171/vhdl/keywordlist.html (95 words here)

Operators

Concatenation (&)

• Both operands must be of same type.
• Like pasting together two operands.

-- If
a : std_logic_vector (2 downto 0)
b : std_logic_vector (1 downto 0)

-- then
a & b 
-- is of type std_logic_vector (5 downto 0)

Ref: https://www.nandland.com/vhdl/examples/example-concatenation-operator.html

Assignment

<=

assign value to a signal

• Takes effect in the next cycle.

:=

assign value to a variable

• Takes effect immediately.

Variables

-- variable var_name : type
variable outvector : std_logic_vector (7 downto 0); 

Records

• Similar to C struct.
• Often used to define new VHDL types.

Syntax:

type <type-name> is record
  <attr1> : <type>;
  <attr2> : <type>;
  ...
  <attrn> : <type>;
end record <type-name>;

Example:

type rec_typ is record
  in_en : std_logic;
  data  : std_logic_vector (7 downto 0);
  out_en: std_logic;
end record rec_typ;

-- use the record
constant inst_rec_type : rec_typ := (in_en  => '0',
                                     data   => '00001001',
                                     out_en => '1);

Another example:

nstate <= (oldver => "00",
           curst => '0');

enum type

type state_t is (IDLE, START, FINISH);

Components

Code that can be reused.

Helps to organize the code.

Reference: link (pdf)

Signals vs variables

Reference

Process

• A VHDL construct containing a set of actions (sequential statements) to be executed sequentially.
• The process itself is a concurrent statement.

Example:

process is
begin
  sign <= sign + 1;
  wait for 10 ns;
end process;

Sensitivity list

• List of signals for which a state change would cause the body of process to be executed.
• ie, the signals that the process is 'sensitive' to.

others

We can set/reset values of a few bits of a bit-vector and then set/reset the remaining bits to some value at once using others.

bv : std_logic_vector (7 downto 0);
bv <= (2      => '1',
       0      => '1',
       others => '0');
-- bit 2 and 0 are set to 1 and all others to 0.
-- ie, bv now has 00000101 as its value.

Gaisler style

Ref: link

• Consists of 2-process entities.
• Each consists of two processes:
  • Combinatory logic process (ie, asynchronous)
  • Sequential logic process (deals register states)

            Combinational
        +-----------------+
 d--→-->|   q = fq(d, r)  |-------> q
    +-->| r_in = fr(d, r) |--→--+
    |   +-----------------+     |
  r ↑                           ↓ r_in
    |   +-----------------+     |
    +-←-|     r = r_in    |--←--+
clk--->-|                 |
        +-----------------+
             Sequential

The sequential component merely copies the value of r_in generated by the combinational process to the register at the start of the next clock cycle.

Consider an example of an 8 bit counter, where:

• load signal enabled to load data value to counter from where counting should start.
• count signal enabled to continue counting.

library ieee;
use ieee.std_logic_1164.all;

entity count8 is
  port(
    clk: in std_logic;
    d: in std_logic_vector (7 downto 0);
    q: out std_logic_vector (7 downto 0);
  );
end count8;

architecture count8_arch is
  signal r, r_in : std_logic_vector (7 downto 0);
begin
  comb: process(load, count, d, r) is
    variable tmp : std_logic_vector (7 downto 0);
  begin
    if load = '1' then
      tmp := d;
    elsif count = '1' then
      tmp := r + 1;
    else
      tmp := r;
    end if;
    r_in <= tmp;
    q <= r;
  end process;

  seq: process(clk)
  begin
    if rising_edge(clk) then
      r <= r_in;
    end if;
  end process;
end count8_arch;

We can do the same using record types:

Packages

An example:

-- https://www.ics.uci.edu/~jmoorkan/vhdlref/function.html
package refpack is
  function parity (x : std_logic_vector)
                  return std_logic;
end refpack;

package body refpack is
  function parity (x : std_logic_vector)
                  return std_logic is
  begin
    -- function body
  end parity;

end refpack;

case ('switch') statement

Syntax:

case <expression> is
  when <const> => 
    ...
  when <const> => 
     ...
end case;

Example:

case a_const is
  when "00" =>
    a_var := 0;
  when "01" =>
    a_var := 1;
  when "10" =>
    a_var := 2;
end case;

Procedure

• Like functions but doesn't have to return any value or can return multiple values??.

Functions

• May contain any sequential statement except signal assignment and wait.
• Functions can have only input parameters, so the mode of args (ie, out~/~in) needn't be mentioned.
• Got to return some value (otherwise use a procedure). ref
• Equivalent to combinatory logic. Cannot replace code containing events or delays.
• TODO VHDL-93 functions may be declared as pure or impure.

Syntax:

function function_name (args: arg_types) ret_type is
  declarations
begin
  sequential statements
end function_name;

Example:

-- Boolean NOT
function cust_not (val: std_logic)
                  return std_logic is
begin
  if val = '1' then
    return '0';
  else
    return '1';
  end if;
end function cust_not;

VHDL vs C

if statement

Example:

if load = '1' then
  tmp := r + 1;
elsif count = '1' then
  tmp := r - 1;
else
  tmp := 1;
end if;

Loops

-- find first set bit
variable vec : std_logic_vector(7 downto 0);
variable first : natural;

for i in vec'range loop
  if vec(i) = '1' then
    first := i;
    exit;  -- break statement
  end if;
end loop;

std_logic_1164

• VHDL 1993 onwards.
• Expanded in VHDL 2008
• only logical operations are defined on these types.

Operations

Operators available in this package include:

std_logic_vector

Like an array of std_logic elements.

-- Vector of 8 bits in each case

-- MSB is in the beginning.
-- Better use this form to avoid confusion
signal a : std_logic_vector (7 downto 0);

-- MSB is at the end.
signal b : std_logic_vector (0 to 7);

-- Indexing a bitvector
-- Get 4th element of a vector
b(4)

Extract specific bit positions

• vec(0): bit 0
• vec(9 downto 7): bits 9,8,7
• vec(1 to 3): bits 1,2,3

Ref: link

Types

• U: uninitialized
• X: forcing unknown
• 0: forcing 0
• 1: forcing 1
• Z: high impedance (tri-state)
• W: weak unknown
• L: weak 0
• H: weak 1
• -: don't care

Source: http://people.sabanciuniv.edu/erkays/el310/ch09.pdf

Explained

• 'Forcing' means that the the signal is driven by a circuit with a regular driving current. [1][1]
• Only 0, 1 and Z find practical use in synthesis these days.

Moore machine

Bit vector representation

numeric_std

• ieee.numeric_std
• Provides efficient implementation of operations like +, -, comparison, etc.

Syntax examples

Assignment after a delay

Although practically, it is quite impossible to construct a circuit with an exact delay since many factors are at play:

• device technology
• routing
• fabrication process
• operation environment

y <= a + b + 1 after 10 ns;
-- means that whenever a or b changes, the expression a+b+1 is evaluated
-- and its value is assigned to y after a delay of 10ns.

Closed feedback loop (bad!)

• A variable is being used to calculate its own next value.
• Considered bad practice. Better avoided.
  • Because, it becomes sensitive to internal propagation delays and might lead to race condition.
  • Confuses synthesis software.
  • Complicates verification and testing.
• Presence of a closed feedback loop => circuit is no longer combinational.

q <= (q and (not en)) or (d and en);
-- keep value of q unchanged if en is 0.
-- Otherwise use d to set q

Conditional assignment

signal_name <= value_expr_1 when boolean_expr_1 else
               value_expr_2 when boolean_expr_2 else
               ...
               value_expr_n;

Examples

4:1 MUX

library ieee;
use ieee.std_logic_1164.all;

entity mux41 is
  port(
    a, b, c, d: in std_logic_vector(7 downto 0);  -- input lines
    s: in std_logic_vector(1 downto 0);           -- select lines (2)
    o: out std_logic_vector(7 downto 0)           -- output line
  );
end mux41;

architecture mux41_arch is
begin
  o <= a when (s="00") else
       b when (s="01") else
       c when (s="10") else
       d;
end mux41_arch;

2:4 decoder

library ieee;
use ieee.std_logic_1164.all;

entity decoder is
  port(
    s: in std_logic_vector(1 downto 0);
    o: out std_logic_vector(3 downto 0)
  );
end decoder;

architecture decoder_arch is
begin
  o <= "0001" when (s="00") else
       "0010" when (s="01") else
       "0100" when (s="10") else
       "1000";
end decoder_arch;

4:2 priority encoder

library ieee;
use ieee.std_logic_1164.all;

entity prio42 is
  port(
    r: in std_logic_vector(3 downto 0);
    code: out std_logic_vector(1 downto 0);
    active: out std_logic
  );
end piro42;

architecture prio42_arch is
begin
    code <= "11" when (r(3)='1') else
        "10" when (r(2)='1') else
        "01" when (r(1)='1')
        "00";

    -- Not sure if the following line would've been okay.
    -- active <= '0' when (r="0000") else '1';

    active <= r(3) or r(2) or r(1) or r(0);
end prio42_arch;

Simple ALU

library ieee;
use ieee.std_logic_1164.all;

entity alu is
  port(
    ctrl: in std_logic_vector(2 downto 0);
    src1, src0: in std_logic_vector(7 downto 0);
    result: out std_logic_vector(7 downto 0);
  );
end alu;

architecture alu_arch is
  signal sum, diff, inc: std_logic_vector(7 downto 0);
begin
  inc <= src0 + 1
  ctrl <= src0 + 1 when
end alu_arch;

Terms

• Delta cycle
  • Applicable only during simulation.
  • Doesn't affect synthesized circuit.
• Delta delay
  • An infinitesimaly small delay after which assignments to signals happen in VHDL by default. ie, unless a delay amount is explicitly specified.
  • Wikipedia
• package

Compilation and simulation

Three phases in simulation of VHDL code:

1. Analysis (compilation)
2. Elaboration
3. Simulation

Analysis

• VHDL compiler is also known as an analyzer.
• Check if code conforms to syntax and semantics. If okay, generates intermediate code.
  • This intermediate code can be used by simulators and synthesizers, after some processing if needed.

Elaboration

• Converts the intermediate code generated as a result of analysis to a form that can be used by simulators.
• A driver is created for each signal.
  • Each driver holds the current value and a queue of future values of the signal associated with it.

Simulation

• Consists of an initialization phase and the actual simulation.
• Simulation commands accepted by the simulator control the simulation.

Tips

• wait statement cannot appear outside process-es.
• if statements cannot appear outside process-es.
• Writing test benches always takes more time than writing the design.

Leave a component port disconnected

Ports can be left disconnected while doing port map on components. Use open.

ADDER2: HALFADD port map
  (B=>Y,A=>X,SUM=>S,CARRY=>open);

Reference: https://www.ics.uci.edu/~jmoorkan/vhdlref/compinst.html

Non-standard packages to avoid

See more

use ieee.numeric_std.all;
-- use ieee.std_logic_arith.all;

Type conversion for std_logic_vector

Reference ⁴

       to_integer()  +--------+   std_logic_vector()           
     +---------------| signed |-------------------+            
     |               +--------+                   |            
     |                ^      ^                    |                
     |                |      |                    |                
     |     to_signed()|      |signed()            |                
     |                |      |                    |                
     V                |      |                    V                
+---------+           |      |           +------------------+
|         |-----------+      +-----------|                  |
| integer |                              | std_logic_vector |
|         |-----------+      +-----------|                  |
+---------+           |      |           +------------------+
     ^                |      |                    ^                
     |                |      |                    |                
     |   to_unsigned()|      |unsigned()          |                
     |                |      |                    |                
     |                V      V                    |                
     |              +----------+                  |             
     +--------------| unsigned |------------------+             
       to_integer() +----------+  std_logic_vector()

<------------------------>  <-------------------------------->
   Conversion functions                Type cast

Acronyms

• LRM: Language Reference Manual.
  • ie, the VHDL standard (IEEE Std 1076-2008 seems to be the latest)

More

• generic
• attribute
• scalar types
• comparison operators
• Linting tool:
  • Style checks: ghdl -s --std=08 file.vhdl
  • Logical error checks: https://github.com/m-kru/go-hdl

Glossary

General

ASIC

Application Specific Integrated Circuit

Synthesis

• A process by which an abstract specification of desired circuit behaviour (typically at RTL level) is turned into a design implementation using logic gates.
• VHDL => source is compiled and mapped into an implementation technology like FPGA or ASIC.
  • Not all VHDL constructs are suitable for synthesis though.
  • Eg: Stuff that explicitly mention timing (like wait for 10 ns) are not synthesisable though they can be used during simulation.

Register Transfer Notation (RTL)

References

• RTL hardware design using VHDL by Pong P. Chu
• Digital systems design using VHDL by Charles H. Roth jr and Lizy Kurian John
• IEEE standard VHDL Language reference manual (IEEE Std 1076, 2000 edition)

Doubts

• if a signal appears in the sensitivity list of multiple processes, in which order will the process blocks be run?
  • In the case of simulation, it's implementation defined.