(Jottings made while scouring the internet to get familiar with EDA)
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- BUFG: Global buffer?
- aka Clock buffer.
- Takes a signal as input and connect to a clock net
- Clock net: Network of wires and buffers optimized for routing clock signals
- CPLD: Complex Programmable Logic Device
- PLD with complexity between PAL and FPGA
- Macrocell: Building blocks of CPLD
- Each macrocell implements DNF expressions
- Timing constraints
- MMCM: Mixed Mode Clock Manager
- IOB: Input Output Block
- Interface between FPGA and external circuits
- Typically grouped into multiple IOB banks.
- Ultra RAM (©): a kind of non-volatile memory
- Architecture of Versal devices ??
- '288Kb, single-clock, synchronous memory blocks'
- 8 times capacity of a block RAM
- Block RAM (BRAM)
- aka embedded memory, aka Embedded Block RAM (EBR)
- DSP: Digital Signal Processors
- LUT: Look Up Table
- MRMAC: Multi-Rate Ethernet MAC
- where MAC is Medium Access Control
- OpenCL: a framework for 'hetergeneous computing'. Like CUDA.
- To distribute work over GPUs, CPUs, DSPs, FPGAs
- Need for FPGA
- Low latency. Like processing data streams in real-time.
- Seperation into behavioural, structural, gate-level designs is a relic of the past? link
- peak in vivado synthesis: maximum memory used by the process ʳ
- gain in vivado synthesis
- PLL: Phase Locked Loop ??
- Clock divider: Circuit creating lower frequency clock from another clock
- SPI flash
- SPI: Serial Peripheral Interface
- Allows two chips to communicate. Needs 4 wires between them.ʳ
- QSPI: Quad Serial Peripheral Interface
- For communicating with an external flash memory via SPI ??
- Parallel data lines
- Cortex-M3: A 32-bit RISC ARM processor core design
- Intended among other things to be used with FPGAs
- Processor vs Processor core: Processor can have many cores
- SystemVerilog vs verilog
- SystemVerilog is a superset of verilog
- PSRAM: Pseudo-Static RAM
- High density of DRAM but with ease of use of SRAM ??
- GPIO: General Purpose IO pin
- FPGA has only LUT4 but design shows LUT5,6,7, etc. No problem if there are muxes which can combine LUT4 to become bigger LUTs.
- Carry chain in FPGA:
- ALUT (Intel-only??): Adaptive LUT
- ALM (Intel-only??): Adaptive Logic Module
- AMBA: Advanced Microcontroller Bus Architecture
- For connecting functional blocks in an SoC
- Advanced eXtensible Interface (AXI): part of AMBA3
- From ARM
- Wishbone: Like AMBA, but free and open
- Barrel shifter
- Crossbar
- NIOS: Altera specific softcore processor design
- PCIe: Peripheral Component Interconnect express
- 'Serial, computer expansion bus standard'
- Commonly used to connect components like sound and graphics cards to motherboard
- I2C: aka IIC
- Inter-Integrated Circuit
- Commonly used to attach low speed peripheral ICs to processors/microcontrollers
- LPDDR: Low-Power Double Data Rate
- A type of SDRAM
- For mobile devices
- Different from DDR standards
- EMMC: Embedded Mulit-Media card
- Used for storage
- Like a memory card ??
- Banks in FPGA
- Pull-up port: pin that is high when not driven
- Shadow RAM:
- A portion of ROM is copied to RAM for faster access
- Eg: BIOS may be loaded onto RAM during booting
- Sign-off: A term used to indicate the set of verification activities that is done before a design is taped out
- MBIST: Memory Built-In Self Test
- LBIST: Logic Built-In Self Test
- DFT: Design-for-Test
- PMU (in ARM): Performance Monitoring Unit
- AMU (in ARM): Activity Monitoring Unit
| Refresh not needed |
Refresh needed |
| Expensive |
Cheaper |
| Less storage capacity |
Higher storage |
- Floorplaning vs placement
- Floorplanning primary deals with placement of larger blocks ??
- Placement arranges the smaller components around the large blocks ??
- IP generators
- ATPG: Automatic Test Pattern Generation
- Data path
- Accelera: a organization maintaining standards related to EDA
- Clock gating
- A way to reduce dynamic power consumption
- Disables (or stop switching??) parts of circuit not being used.
- Clock won't be delivered to those parts
- Disadvantage: More logic need to implement clock gating
- Power consumption:
- Switching power
- Leakage current
- HSTL: High Speed Transceiver Logic
- SSTL: Stub Series Terminator Logic
- HSUL: High Speed Unterminated Logic
- LVDS: Low Voltage Differential Signalling
- Technology for high speed data transmission over copper wire
- Low power, cheap, high speed
- Netlist obfuscation: Used to 'protect' proprietary IPs
- SSI: Stacked Silicon Interconnect
- Multiple slices stacked together
Unknown:
- Clock region
- Clock domain crossing
- Clock tree
- Reference operating voltage
- Setup and hold time ??
- DRC (Design Rule Check)
- How to undo soldering
- IO pin planning (vivado)
- Clock analysis (vivado)
Power consumption estimation (Vivado)
https://www.xilinx.com/video/hardware/power-estimation-analysis-using-vivado.html
Two options:
- Vector based
- Ideally requires a simulation activity file (as a SAIF/VCD file)
- More accurate
- Non-vector based
Floorplanning
- pblocks: Physical blocks
- 'Containers' used in floorplanning
Slices in FPGAs
- Each slice has a set number resources like registers, LUTs and MUXes
- Not the same as CLB (Configurable Logic Block)
Xilinx specific:
- SLICEL: Used only for logic
- SLICEM: Used as memory or for logic
- BEL: Basic Element of Logic
- Within a CLB ??
- Smallest indivisible component that can be used to implement logic
- BD: Block design
- File formats:
- ngc: netlist generator code
- Used in the older ISE
- EDIF for vivado
- xco: core generator
- xci: core generated from an xco ?? Or is it built-in IPs of vivado?
- xdc: constraints file
- Xilinx Design Constraints
- UCF: a legacy constraints file format used by Xilinx
.dcp files: Design checkpoints in vivado
- XPM: Xilinx Parameterized Macros
__SYNTHESIS__: a macro in Vivado HLS that is true if design is being synthesized ʳ- Unisim: Unified simulation primitives
- Related to low level primitives of Xilinx FPGAs
- Parallel synthesis criteria (Vivado)
Devices, interfaces, protocols etc
- TF card: TransFlash card
- An older 'form' of microSD cards ??
- Functionally identical to microSD cards ʷ
- UART: Universal Asynchronous Receiver Transmitter
- JTAG
create_clock in sdc/xdc file
Example from default xdc file for Pynq-Z2:
create_clock -add -name clk -period 8.00 -waveform {0 4} [get_ports { clk }];
period
period is in ns.
1 1
ν = ──────── = ─────── Hz = 125MHz
period 8*10⁻⁹
- Specify rise and fall times of clock (in nano-seconds)
- Can make positive and negative parts of a cycle equal like in above example with
{0 4}.
- Clock can be made to rise and fall multiple times as well??
Another example:
# Clock rises at step 2ns and falls at step 4ns
create_clock –period 7 –waveform {2 4} [get_ports {CK3}]
Could it be like this??:
| | ┏━━━━━━━┓ | | |
| | ┃ | ┃ | | |
|---|---┃---|---┃---|---|---|
| | ┃ | ┃ | | |
|━━━━━━━┛ | ┗━━━━━━━━━━━|
0 1 2 3 4 5 6 7
See:
False path in sdc/xdc file
set_false_path- Exclude a path from timing analysis
- For paths that exists in the design, but are not functional or doesn't need to timed. ˡ
https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/false-paths-set-false-path.html
Breadboard stuff
- Solder bridge
- Soldering iron and tin wire (solder)
- Chisel tip vs conical tip
- Might take 5 minutes to get heated
- Solder: Maybe a mix of lead and tin
- Something with melting point low enough for the soldering iron to melt
- Remember that lead is not good for health
- Size of solder in inches
- Flux core solder
- Flux: 'Helps the solder flow'
- Methods for desoldering: Removing soldering
- Solder wick (aka solder braid): a braid of thin copper wires
- Solder sucker
- Removing flux from board: Spray isopropyl alcohol
- Flush cutter: Clippers to cut off leftover length of pins
- Heat shrink: Tube-like thing used to insulate exposed wire
- Selective vs wave soldering
- Tombstoning
- Jumper wires
- Debouncing: For physical switches
- A single press would look like multiple presses
- Debounce time: Time taken for switch value to become stable
- Header pins
DBT: Can soldering be undone
Random stuff
- Kinds of sound synthesis:
- Subtractive
- Additive
- Physical modeling
- FM synthesis
- Granular synthesis
- Wavetable synthesis
- Inferred latch problem
- Latches are usually not desirable in a design to be loaded to FPGA
Tidbits
Chip foundries:
- TSMC (Taiwan): Most chips seem to be fabricated by them
- Others:
- SMIC (China)
- GlobalFoundries (USA?):
- UMC (Taiwan)
Terms in EDA
- Slack: Difference between time needed for signal to propogate and available time to propagate
- Negative slack: Bad. There isn't enough clock
- Positive slack: Okay, but better not be too big either
- TNS: Total Negative Slack
- Total of all negative slacks ʳ
- Does not include any positive slacks ʳ
- WNS: Worst Negative Slack
- Worst of all individual negative slacks
- (Confusing name… Slack need not actually negative here.)
- ie, slack of critical path ˡ
- If it's negative, timing constraint is not met. Otherwise okay.
- 'The more negative, the worse it is' ʳ
- Primitives: Smallest component that we can configure in an FPGA
- DFFE: A primitive. D flip flop with clock enable.
- Delta cycle
- Non-time consuming cycles added for modeling properly while a design is being simulated
- https://vhdlwhiz.com/delta-cycles-explained/
- To make up for hardware being inherently parallel whereas computer simulating it leans more towards sequential execution.
- Duty cycle (power electronics): Fraction of a period for which a signal under consideration is active
- Sensitivity list: List of signals changes to which trigger running of a process block
- DUT: Design Under Test
- Power domain: ??
- Hard macro vs soft macro
Processes in EDA
- Synthesis: HDL converted to gate level netlist
- Implementation: Does placing and routing for target board using information in netlist
- Power usage information can be figured out only after implementation
- Elaboration:
- First phase of synthesis.
- Output is a technology independent netlist.
- LVS (Layout vs Schematic checking)
- Techmapping
- Floorplanning vs placement
- Placement: Deciding where to place circuit components
- Routing: Connecting circuit components after they've been placed
- Post-implementation functional simulation (vivado term)
- EDIF (Electornic Design Interchange Format)
- For EDA
- Vendor-neutral
- S-expression based
- Gerber: for PCB designs
- GDSII: Standard format used to share a design's layout info
- A binary data format (for ASIC)
- Format of files used to store designs
- aka GDS2
- Foundaries are given GDSII files for fabrication
- GDSII stream format
- GDS stands for Graphic Design System ??
- OASIS: A newer format similar to GDSII
- Open Artwork System Interchange Standard
- PDK (Process Design Kit)
- Liberty file (
.lib): Liberty timing file
Chip packaging
- DIP: Dual Inline Package
- Leads on opposite sides
- Like in old timer IC chips
- SOIC: Small Outline IC
- Small outline package
- Shorter and narrower than DIP
- QFP: Quad Flat Package
- Leads on all 4 sides of the chip. Like common in microprocessor chips.
- Surface mounted
- Variants: TQFP, LQFP
See:
FPGA vs microcontroller vs GPU
- Microcontroller < GPU < FPGA
- FPGA vs microcontroller
- FPGA vs GPU
Some historical stuff
- PAL: Programmable Array Logic
- Programmable AND array followed by a fixed OR array
- PLA: Programmable Logic Array
- Programmable AND array followed by a programmable OR array
Not general
- EDA tools:
- Innovus (Cadence)
- Quartus (Intel)
- Questa (Siemens)
- Vivado (AMD)
tcl scripting
Doubts
- Can we specify that a particular component needs to be mapped to SRAM or DRAM in HDLs?
- Why are UVM models copyrighted? Is it too difficult to make?
- PoR: Power-on-Reset
- In FPGAs. Not in ASIC ??
- How to do this in HDL
- What are 18x18 multipliers
- How to use PLL in FPGAs
- Difference between BRAM and DRAM
- BRAM is internal memory, but DRAM is external ??
- BRAM is a kind of SRAM ??
- SRAMs in general, can be external
- Clock divider circuit is straightforward. What about clock 'multiplier'?
