EDA and related stuff

(Jottings made while scouring the internet to get familiar with EDA)

—

BUFG: Global buffer?
- aka Clock buffer.
- Takes a signal as input and connect to a clock net
Clock net: Network of wires and buffers optimized for routing clock signals
CPLD: Complex Programmable Logic Device
- PLD with complexity between PAL and FPGA
Macrocell: Building blocks of CPLD
- Each macrocell implements DNF expressions
Timing constraints
- Files with .sdc and .xdc extensions
- xdc is sdc with some xilinix-specific things added
- https://www.latticesemi.com/en/Blog/2021/06/07/18/52/ImportanceofTimingConstraints
- Setup and hold violations
  - Input to flip flop changes before the flip-flop's setup or hold time has passed.
MMCM: Mixed Mode Clock Manager
IOB: Input Output Block
- Interface between FPGA and external circuits
- Typically grouped into multiple IOB banks.
Ultra RAM (©): a kind of non-volatile memory
- Architecture of Versal devices ??
- '288Kb, single-clock, synchronous memory blocks'
- 8 times capacity of a block RAM
Block RAM (BRAM)
- aka embedded memory, aka Embedded Block RAM (EBR)
DSP: Digital Signal Processors
- http://hunteng.co.uk/info/fpga-or-dsp.htm
- Has to programmed
  - So does an FPGA, right??
- Slower clocks than FPGA capability
LUT: Look Up Table
MRMAC: Multi-Rate Ethernet MAC
- where MAC is Medium Access Control
OpenCL: a framework for 'hetergeneous computing'. Like CUDA.
- To distribute work over GPUs, CPUs, DSPs, FPGAs
Need for FPGA
- Low latency. Like processing data streams in real-time.
Seperation into behavioural, structural, gate-level designs is a relic of the past? link
- Now no longer mutually exclusive
- Safer to distinguish between synthesizable and non-sytheziable designs
- https://electronics.stackexchange.com/questions/63682/difference-between-rtl-and-behavioral-verilog
peak in vivado synthesis: maximum memory used by the process ʳ
gain in vivado synthesis
PLL: Phase Locked Loop ??
- Can be used to increase internal clock speed
- But this increased speed also increases chances of glitches
- https://www.digikey.in/en/maker/projects/introduction-to-fpga-part-9-phaselocked-loop-pll-and-glitches/2028ce62001b4cb69335f48e127fa366
- https://www.techtarget.com/searchnetworking/definition/phase-locked-loop
Clock divider: Circuit creating lower frequency clock from another clock
- aka frequency dividerʷ
SPI flash
- SPI: Serial Peripheral Interface
- Allows two chips to communicate. Needs 4 wires between them.ʳ
QSPI: Quad Serial Peripheral Interface
- For communicating with an external flash memory via SPI ??
- Parallel data lines
Cortex-M3: A 32-bit RISC ARM processor core design
- Intended among other things to be used with FPGAs
Processor vs Processor core: Processor can have many cores
SystemVerilog vs verilog
- SystemVerilog is a superset of verilog
PSRAM: Pseudo-Static RAM
- High density of DRAM but with ease of use of SRAM ??
GPIO: General Purpose IO pin
FPGA has only LUT4 but design shows LUT5,6,7, etc. No problem if there are muxes which can combine LUT4 to become bigger LUTs.
Carry chain in FPGA:
- For efficient arithmetic operations
- https://www.fpga4fun.com/Counters4.html
ALUT (Intel-only??): Adaptive LUT
ALM (Intel-only??): Adaptive Logic Module
AMBA: Advanced Microcontroller Bus Architecture
- For connecting functional blocks in an SoC
- Advanced eXtensible Interface (AXI): part of AMBA3
- From ARM
Wishbone: Like AMBA, but free and open
Barrel shifter
Crossbar
NIOS: Altera specific softcore processor design
PCIe: Peripheral Component Interconnect express
- 'Serial, computer expansion bus standard'
- Commonly used to connect components like sound and graphics cards to motherboard
I2C: aka IIC
- Inter-Integrated Circuit
- Commonly used to attach low speed peripheral ICs to processors/microcontrollers
LPDDR: Low-Power Double Data Rate
- A type of SDRAM
- For mobile devices
- Different from DDR standards
EMMC: Embedded Mulit-Media card
- Used for storage
- Like a memory card ??
Banks in FPGA
- IO blocks spread across different banks
- Makes FPGA manufacturing easier and cheaper
- Different parts of the FPGA might have different requirements
  - Eg: Analog and digital parts might need different gnd.
- https://www.edaboard.com/threads/what-is-a-bank-in-fpga.78952/
Pull-up port: pin that is high when not driven
- Realized by means of a weak pull-up resistor ??
  - 'Pulls up' the pin to a certain voltage
- Avoids the pin being a 'floating' or undefined value when not driven
- https://electronics.stackexchange.com/questions/369189/pull-up-fpga-pull-down
Shadow RAM:
- A portion of ROM is copied to RAM for faster access
- Eg: BIOS may be loaded onto RAM during booting
Sign-off: A term used to indicate the set of verification activities that is done before a design is taped out
- https://en.wikipedia.org/wiki/Signoff_(electronic_design_automation)
MBIST: Memory Built-In Self Test
- A self-testing circuit is incorporated into the memory chip
- Writes patterns to memory and check if the result is acceptable
- Tests whether memory gets faulty ??
- https://chipedge.com/mbist-in-vlsi-ensuring-better-quality-chips/
LBIST: Logic Built-In Self Test
- Self-test logic without external equipment
- https://vlsitutorials.com/logic-built-in-self-test-lbist/
DFT: Design-for-Test

PMU (in ARM): Performance Monitoring Unit
- https://developer.arm.com/documentation/ka004659/latest/
- https://cloud.google.com/compute/docs/pmu-overview
AMU (in ARM): Activity Monitoring Unit
- https://developer.arm.com/documentation/ka004659/latest/

SRAM	DRAM
Refresh not needed	Refresh needed
Expensive	Cheaper
Less storage capacity	Higher storage

Floorplaning vs placement
- Floorplanning primary deals with placement of larger blocks ??
- Placement arranges the smaller components around the large blocks ??
IP generators
ATPG: Automatic Test Pattern Generation
- Only for ASIC?
Data path
Accelera: a organization maintaining standards related to EDA
Clock gating
- A way to reduce dynamic power consumption
- Disables (or stop switching??) parts of circuit not being used.
- Clock won't be delivered to those parts
- Disadvantage: More logic need to implement clock gating
Power consumption:
- Switching power
- Leakage current
HSTL: High Speed Transceiver Logic
- A technology independent standard for signalling ??
- https://www.intel.com/content/www/us/en/docs/programmable/683375/current/differential-hstl-sstl-and-hsul-termination.html
SSTL: Stub Series Terminator Logic
- Standards related to driving wires
- Often used for DDRAM and SRAM modules
- https://en.wikipedia.org/wiki/Stub_Series_Terminated_Logic
HSUL: High Speed Unterminated Logic
LVDS: Low Voltage Differential Signalling
- Technology for high speed data transmission over copper wire
- Low power, cheap, high speed
Netlist obfuscation: Used to 'protect' proprietary IPs

SSI: Stacked Silicon Interconnect
- Multiple slices stacked together

Unknown:

Clock region
Clock domain crossing
Clock tree
Reference operating voltage
Setup and hold time ??
- https://vhdlwhiz.com/terminology/setup-and-hold-time/
DRC (Design Rule Check)
How to undo soldering
IO pin planning (vivado)
Clock analysis (vivado)

Power consumption estimation (Vivado)

https://www.xilinx.com/video/hardware/power-estimation-analysis-using-vivado.html

Two options:

Vector based
- Ideally requires a simulation activity file (as a SAIF/VCD file)
- More accurate
Non-vector based
- Relies on heuristics

Floorplanning

pblocks: Physical blocks
- 'Containers' used in floorplanning

Slices in FPGAs

Each slice has a set number resources like registers, LUTs and MUXes
Not the same as CLB (Configurable Logic Block)
- A CLB may have multiple slices
- Eg: SLICEL and SLICEM in Xilinx Ultrascale
- https://digilent.com/blog/fpga-configurable-logic-block

Xilinx specific:

SLICEL: Used only for logic
SLICEM: Used as memory or for logic
BEL: Basic Element of Logic
- Within a CLB ??
- Smallest indivisible component that can be used to implement logic
BD: Block design

File formats:
- ngc: netlist generator code
  - Used in the older ISE
  - EDIF for vivado
- xco: core generator
- xci: core generated from an xco ?? Or is it built-in IPs of vivado?
- xdc: constraints file
  - Xilinx Design Constraints
- UCF: a legacy constraints file format used by Xilinx
- .dcp files: Design checkpoints in vivado
XPM: Xilinx Parameterized Macros
__SYNTHESIS__: a macro in Vivado HLS that is true if design is being synthesized ʳ
Unisim: Unified simulation primitives
- Related to low level primitives of Xilinx FPGAs
Parallel synthesis criteria (Vivado)
- Provision for vivado to use multiple processor cores
- The warning '[Synth 8-7080] Parallel synthesis criteria is not met' means that vivado decided not to use parallel threads for the current design Likely if the design is monolithic.
- https://stackoverflow.com/questions/79563001/vivado-2024-1-warning-synth-8-7080-parallel-synthesis-criteria-is-not-met
- https://adaptivesupport.amd.com/s/question/0D52E000079rMivSAE/how-to-avoid-vivado-warning-parallel-synthesis-criteria-is-not-met?language=en_US

Devices, interfaces, protocols etc

TF card: TransFlash card
- An older 'form' of microSD cards ??
- Functionally identical to microSD cards ʷ
UART: Universal Asynchronous Receiver Transmitter
JTAG
- https://www.fpga4fun.com/JTAG1.html
- Allows probing pins without messing around with it physically
- Can kind of 'hijack' the pins
- Joint Test Action Group

`create_clock` in sdc/xdc file

Example from default xdc file for Pynq-Z2:

create_clock -add -name clk -period 8.00 -waveform {0 4} [get_ports { clk }];

period

period is in ns.

       1          1
ν = ──────── = ─────── Hz = 125MHz
     period     8*10⁻⁹

waveform

Specify rise and fall times of clock (in nano-seconds)
Can make positive and negative parts of a cycle equal like in above example with {0 4}.
Clock can be made to rise and fall multiple times as well??

Another example:

# Clock rises at step 2ns and falls at step 4ns
create_clock –period 7 –waveform {2 4} [get_ports {CK3}]

Could it be like this??:

|   |   ┏━━━━━━━┓   |   |   |
|   |   ┃   |   ┃   |   |   |
|---|---┃---|---┃---|---|---|
|   |   ┃   |   ┃   |   |   |
|━━━━━━━┛   |   ┗━━━━━━━━━━━|
0   1   2   3   4   5   6   7

See:

False path in sdc/xdc file

set_false_path
Exclude a path from timing analysis
For paths that exists in the design, but are not functional or doesn't need to timed. ˡ

https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/false-paths-set-false-path.html

Breadboard stuff

Solder bridge
- Excessive soldering causing two pins to get connected
- https://resources.pcb.cadence.com/blog/2022-what-is-a-solder-bridge
Soldering iron and tin wire (solder)
- Chisel tip vs conical tip
- Might take 5 minutes to get heated
Solder: Maybe a mix of lead and tin
- Something with melting point low enough for the soldering iron to melt
- Remember that lead is not good for health
- Size of solder in inches
- Flux core solder
Flux: 'Helps the solder flow'
- https://www.chemtronics.com/essential-guide-to-flux-for-soldering-electronics
Methods for desoldering: Removing soldering
- Solder wick (aka solder braid): a braid of thin copper wires
  - Adding flux can help.
  - DBT: Can we reuse solder wick?
  - https://kunkune.co.uk/blog/how-to-use-solder-wick/
- Solder sucker
Removing flux from board: Spray isopropyl alcohol
Flush cutter: Clippers to cut off leftover length of pins
Heat shrink: Tube-like thing used to insulate exposed wire
- Looks like the tube 'hugs' the wire once it is heated
- https://en.wikipedia.org/wiki/Heat-shrink_tubing#/media/File:Schrumpfschlauch_animated_modified.gif
- Heat gun could be used to do the heating
Selective vs wave soldering
Tombstoning
Jumper wires
Debouncing: For physical switches
- A single press would look like multiple presses
- Debounce time: Time taken for switch value to become stable
Header pins
- https://riverdi.com/blog/header-pins-in-electronics

DBT: Can soldering be undone

Random stuff

Kinds of sound synthesis:
- Subtractive
- Additive
- Physical modeling
- FM synthesis
- Granular synthesis
- Wavetable synthesis
Inferred latch problem
- Latches are usually not desirable in a design to be loaded to FPGA

Tidbits

Chip foundries:

TSMC (Taiwan): Most chips seem to be fabricated by them
Others:
- SMIC (China)
- GlobalFoundries (USA?):
- UMC (Taiwan)

Terms in EDA

Slack: Difference between time needed for signal to propogate and available time to propagate
- Negative slack: Bad. There isn't enough clock
- Positive slack: Okay, but better not be too big either
TNS: Total Negative Slack
- Total of all negative slacks ʳ
  - Does not include any positive slacks ʳ
WNS: Worst Negative Slack
- Worst of all individual negative slacks
- (Confusing name… Slack need not actually negative here.)
- ie, slack of critical path ˡ
- If it's negative, timing constraint is not met. Otherwise okay.
  - 'The more negative, the worse it is' ʳ
Primitives: Smallest component that we can configure in an FPGA
- DFFE: A primitive. D flip flop with clock enable.
Delta cycle
- Non-time consuming cycles added for modeling properly while a design is being simulated
- https://vhdlwhiz.com/delta-cycles-explained/
- To make up for hardware being inherently parallel whereas computer simulating it leans more towards sequential execution.
Duty cycle (power electronics): Fraction of a period for which a signal under consideration is active
Sensitivity list: List of signals changes to which trigger running of a process block
DUT: Design Under Test
Power domain: ??
Hard macro vs soft macro
- Hard macro: already optimized. Is a blackbox
- Soft macro: can be further optimized
- https://chipedge.com/macro-in-vlsi/

Processes in EDA

Synthesis: HDL converted to gate level netlist
Implementation: Does placing and routing for target board using information in netlist
- Power usage information can be figured out only after implementation
Elaboration:
- First phase of synthesis.
- Output is a technology independent netlist.
LVS (Layout vs Schematic checking)
- Compares netlist from schematic (pre place and route?) and netlist from layout (post place and route?)
- See if both netlists correspond to each other
- https://www.synopsys.com/glossary/what-is-layout-versus-schematic-checking.html
- https://www.zerotoasiccourse.com/terminology/lvs/
Techmapping
Floorplanning vs placement
- Floorplanning is 'kind of' like placement but at a higher level?? Placement goes into more detail.
- https://www.edaboard.com/threads/difference-bettewen-floorplanning-and-placement.119533/
Placement: Deciding where to place circuit components
Routing: Connecting circuit components after they've been placed
Post-implementation functional simulation (vivado term)

EDIF (Electornic Design Interchange Format)
- For EDA
- Vendor-neutral
- S-expression based
Gerber: for PCB designs
- Extension: .gbr
GDSII: Standard format used to share a design's layout info
- A binary data format (for ASIC)
- Format of files used to store designs
- aka GDS2
- Foundaries are given GDSII files for fabrication
- GDSII stream format
- GDS stands for Graphic Design System ??
OASIS: A newer format similar to GDSII
- Open Artwork System Interchange Standard
PDK (Process Design Kit)
- Set of files used for fabrication of an IC
- https://www.synopsys.com/glossary/what-is-a-process-design-kit.html
Liberty file (.lib): Liberty timing file
- Has data on timing and power on cell components
- For a standard cell library
- DBT: Does it vary with boards?
- https://www.vlsisystemdesign.com/worried-about-liberty-basics-lets-start-from-ground-zero/
- 'contain all the properties of the cells of a standard cell library, but not the physical design of them.'

Chip packaging

DIP: Dual Inline Package
- Leads on opposite sides
- Like in old timer IC chips
SOIC: Small Outline IC
- Small outline package
- Shorter and narrower than DIP
QFP: Quad Flat Package
- Leads on all 4 sides of the chip. Like common in microprocessor chips.
- Surface mounted
- Variants: TQFP, LQFP