Open source hardware

Tools

• ghdl: VHDL compiler

• nvc: VHDL compiler

• iverilog: verilog/systemverilog compiler

• slang: systemverilog fron -end

  • LSP: https://github.com/hudson-trading/slang-server

• bsc: BlueSpec compiler

• LiteX: For building

  • Only for migen?

• verible: parsing and more for SystemVerilog

  • https://github.com/chipsalliance/verible

• yosys: synthesis

  • synlig: systemverilog with yosys

• bambu: synthesis

• LiveHD: synthesis (WIP as of Dec 2024)

• openFPGALoader

• OpenRAM: SRAM compiler

• f4pga (formerly SymbiFlow)

• KLayout: IC layout viewer and editor

• magic: layout tool

• netgen: LVS (compares netlists)

• IRSIM: a switch-level simulator

• xcircuit: produce schematic diagram of circuits

  • Can also derive netlist from schematic? (schematic capture)

Placement and routing

• nextpnr
  • arachne-pnr is superseded by this
• vtr
• graywolf (Placement only): Inactive??

Static timing analysis:

• OpenTimer
• vesta: Part of qflow

Simulation/testing tools:

• Verilator: Fast simulation for verilog/systemverilog designs
  • Fast because design is compiled to C++ and then run
  • Partial UVM support: https://github.com/chipsalliance/uvm-verilator
• cocotb: a verification framework in python
  • Can be used to simulate with verilator as well?
• pyuvm: UVM via python ??
  • Only a subset of UVM supported
  • Tools that can take advantage of UVM are mostly paid and closed source ??
    • Can use cocotb-verilator-pyuvm combination instead

View wave form:

• gtkwave
• vcd
• wavedrom

Tool chains:

• qflow (ASIC)
• coriolis2 (ASIC)
• openlane2

Netlist layout viewer:

• netlistsvg: Use netlist as json to view as image
• xschem: Schematic editor/viewer

Open source processor designs:

• Ibex: https://github.com/lowRISC/ibex

Other:

• LLVM CIRCT

Misc (haven't tried these):

• Hog: Version control for hardware design files
  • https://hog.readthedocs.io/
• Silicon compiler: https://www.siliconcompiler.com/

HDLs

'Nouvelle vogue':

• pyRTL
• pyrope
• Clash (Haskell)
• Chisel (Scala)
• hardcaml (OCaml)
• migen
• amaranth (grew out of migen??)
• Spinal-HDL
  • Scala-based

Terms:

• FHDL: Fragmented HDL

Misc

• TL-X: A new paradigm for hardware design ?

  • Something higher level than RTL ?

• HardwareX: An open access journal owned by Elsevier

• OSHWA: Open source hardware assocation

• LTspice

• ngspice

• kicad: PCB design

• qucs

FPGA bitstream documentation projects:

• Project Apicula: Gowin
• Project Trellis: Lattice ECP5
• Project IceStorm: Lattice iCE40
• Project X-Ray: Xilinx 7-series

Companies making boards:

• Arduino
• Raspberry Pi
• AdaFruit

Research languages:

• calyx, filament

Open source friendly boards

• Gowin
  • SiPeed Tang Nano
• Lattice ICE40

Proprietary tools

• Xilinx Vivado
  • Xilinx ISE was there before this.
• Intel Quartus

By the looks of it, these are unnecessarily heavy on memory and not so user friendly.

Designs

• OpenTitan: https://github.com/lowRISC/opentitan/
• riscv-dv: https://github.com/chipsalliance/riscv-dv
  • Random instr generator for risc-v verification
• Corundum: FPGA-based NIC for in-network compute (Verilog)
  • https://github.com/corundum/corundum
• LEON 3: an open source processor design (VHDL)
  • ISA: SPARC V8
  • By Gaisler research
• Shakthi: RISC-V processor designs (Bluespec)
  • From IIT Madras
  • https://gitlab.com/shaktiproject
• openPiton: processor
  • From Princeton
  • https://github.com/PrincetonUniversity/openpiton

More

• https://github.com/ben-marshall/awesome-open-hardware-verification

• https://www.chipsalliance.org/projects/

• wavedrom: javascript app for timing diagrams

  • uses WaveJSON format to store data

• https://opensource.googleblog.com/2021/09/open-source-systemverilog-tools-in-asic-design.html

• Open source laptop: https://github.com/byrantech/laptop

• MNT reform hobbyist laptop: https://source.mnt.re/reform/desktop-reform

• Open source ebook reader: https://www.oddlyspecificobjects.com/projects/openbook/